1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device effectively used for, e.g., a power consumption reduction technique for cutting off power to a logic block in a standby state.
2. Description of the Related Art
Various power consumption reduction techniques have conventionally been adopted in semiconductor integrated circuit devices. For example, a power switch configured to cut off supply of power to a logic block in a standby state may be adopted to reduce power consumption. More specifically, a power switch is provided between a virtual power line as a power source inside a semiconductor integrated circuit device (hereinafter referred to as a virtual power source) and a power source outside the semiconductor integrated circuit device (an external power source), thereby controlling supply of power from the external power source to the virtual power line.
Power is supplied to a logic block in a standby state and an activated logic block from power switches different from each other. Rush current may be generated at an instant when the power switch is turned on to activate a logic block in a standby state. If rush current occurs, a power line voltage of the external power source varies, and supply of power to another activated logic block becomes unstable, which may cause the logic block to malfunction.
For this reason, Japanese Patent Application Laid-Open Publication No. 2008-34667 (hereinafter referred to as Document 1) discloses a technique for preventing rush current. According to the technique in Document 1, a transistor is adopted as a power switch, and a capacitor is connected between a gate and a drain of a transistor, which prevents generation of rush current. Also, according to the technique in Document 1, a control circuit is provided, a time required for a rise in a power line voltage to 100% of a final value is predicted from a difference between a time which elapses before the power line voltage rises to 30% and a time which elapses before the power line voltage rises to 60%, and a transistor is fully turned on. The configuration allows reliable power supply and achieves less power consumption.
However, fine adjustment for controlling a rise in power line voltage to be gentle is extremely difficult in control of power switches to be collectively controlled using capacitors, and control of rush current is difficult for the technique in Document 1. In addition, the technique in Document 1 requires a circuit for predicting, from a rise in power line voltage, when to fully turn on a main switch and suffers from the problem of a large circuit scale.